Capacitive loads are often found in the form of piezoelectric actuators, such as piezoelectric speakers or motors for driving mechanical components. Typically, the capacitive loads are relatively small, e.g., on the order of 2 nF. Thus, driver circuits for driving capacitive loads are often designed without taking into account the possibility that the drivers may be connected to loads that are of greater capacitance than the drivers can handle. As the load capacitance increases, so does the power required to drive the capacitance. If the power exceeds the current handling capabilities of the driver, damage may occur.
FIG. 1 shows an example of a conventional H-bridge driver 10 formed using CMOS elements. Each terminal of a capacitive load 20 is connected to a respective resistor 5, which receives an input signal from a source-drain connection of a PFET-NFET transistor pair. Alternatively, the capacitor terminals may be connected directly to the source-drain connection without intervening resistors. One transistor pair consists of a PFET 12 and an NFET 16. Another pair consists of a PFET 14 and an NFET 18. The PFETs 12/14 operate as pull-up devices and are connected to a power supply signal Vdd. The NFETs operate as pull-down devices and are connected to a ground signal Vss. Depending on the gate inputs supplied to the transistors 12/14/16/18, the load 20 may be driven in any number of ways. For example, the PFET 12 may be switched on in combination with the NFET 16, e.g., by first turning the PFET 12 on to develop a voltage (e.g., Vdd) at a source-drain connection Vout_1, then turning PFET 12 off while turning NFET 16 on to provide a current path to Vss. Alternatively, the PFET 14 may be switched on in combination with the NFET 18, e.g., by turning the PFET 14 on, then off while turning NFET 18 on. In either of these configurations, current is supplied across the terminals of the load 20. If the capacitance of the load 20 is too large, the current may exceed the handling capabilities of the driver 10, and cause permanent damage to one or more of the transistors 12/14/16/18.
In addition to high capacitance, another problem to which the present invention is directed is short circuits. In FIG. 1, if the PFET 12 and the NFET 18 are switched on while the terminals of the capacitor are shorted, this leads to a dangerous condition in which Vdd is essentially connected directly to Vss through low ohmic drivers. Consequently, a large current develops through the transistors 12/18 which, as pointed out above, can lead to permanent damage. Thus, there is a need in the art for techniques that prevent damage to drivers, and in particular, damage arising from attempts to drive high capacitive loads.
FIG. 2 shows a plot of the output current of the driver 10 of FIG. 1 versus time. A curve 23 may correspond to a hypothetical current measured through either of the two source-drain connections labeled Vout_1 and Vout_2 in FIG. 1. A curve 21 may correspond to a hypothetical short circuit condition in which the current at the source-drain connection rapidly rises to a maximum and then remains constant. Curve 23 may be related to capacitor charge in that the current rapidly rises as the load 20 is charged, then saturates before slowly decreasing (corresponding to a transition from transistor saturation to triode region operation when the capacitor voltage is charged to a nearly Vdd-level voltage, as measured at Vout_1 or Vout_2).
As evident from the curves 21 and 23, the current goes high and saturates in both cases, so that it is not possible to distinguish the short circuit condition simply by detecting a high current. However, as explained below, selection of appropriate threshold detection levels in combination with detection timing allows for proper short circuit detection.
Additionally, the rate at which the current in curve 23 decays is a function of capacitor size and of the total series resistance connected to the capacitor (e.g., FET resistances plus any additional series resistances). If the load 20 is relatively small, then the current should decay quickly. Thus, as explained in connection with the exemplary embodiments of the present invention, current and/or voltage at the output, e.g., the source-drain connection Vout_1, can be used to detect capacitor size.